Invention relates to computer-aided engineering (CAE) tools for system and circuit design, particularly to automation software for providing clock tree/mesh construction concurrently with physical design.
Commercially-available electronic design automation (EDA) software tools provide electronics and system design engineers with conventional means to define and verify functional and physical aspects of circuit and system design. In particular, design functional definition may be represented in so-called netlist or equivalent file, typically including various components and electrical interconnections therein. Moreover, ordinarily, certain designs may include one or more interconnections associated with relatively time-critical signals or datapaths, such as clocking or other synchronized timing signals.
However, physical implementation of designs embodying such critical timing paths may be subject to undesirable signal delay or skewing, for example, arising from interconnect parasitic resistance or capacitance, or other manufacturing implementation related factors. Accordingly, to mitigate or eliminate such undesirable signal effects, known techniques have been detailed to insert buffers, latches or repeaters, or otherwise introduce effectively temporally counter-acting circuit or interconnect elements or modifications in such critical timing paths, particularly directed at so-called clock trees or meshes.
Such known techniques generally contemplate element insertion or re-sizing in serial fashion, i.e., before or after placement of circuit components, such as logic gates and cells. Pre-placement approach is not practical because introduced components, such as buffers, latches, or repeaters, may move during placement. Furthermore, clock tree construction before determining topology, length, and buffering of subject tree may result in overdesigned or improperly designed circuit. Additionally, post-placement approach to clock tree construction is not practical because routing resources are not properly preserved.
For example, by using placement tools available commercially from Cadence Design Systems (San Jose, Calif.), such as Qplace product for initially placing logic gates, and then CTgen product for synthesizing clock tree, final pass of detailed placement is performed subsequently to address apparent design errors, but such conventional methodology offers no means to iterate design back to global optimization placement algorithms.
Invention resides in electronic design system and/or methodology wherein clock tree or mesh construction is optimizable progressively, preferably concurrently with object placement. Generally, clock tree is specified loosely for initial placement, then followed by progressive detailed placement.
In particular, preferred approach provides automated and reliable solution to clock tree/mesh construction, occuring concurrently with placement process so that clock tree wiring and buffering considers and influences placement and wiring of all other objects, such as logic gates, memory elements, macrocells, etc. Hence, in this concurrent manner, clock tree/mesh pre-wiring and pre-buffering may be based on construction of approximate clock tree using partitioning information only, i.e., prior to object placement. Further, present approach provides modified DME-based clock tree topology construction without meandering, and recursive algorithm for buffered clock tree construction.